Conventional data setup/hold timing circuits provide non-variable data setup/hold timing. Data setup is defined as the time the data should be present at an input before a clock signal arrives. Data hold is defined as the time the data should be held at the input after the clock signal arrives.
Referring to FIG. 1, a conventional circuit 10 requiring an aggressive data setup time is shown. The circuit 10 comprises a first circuit, such as an application specific integrated circuit (ASIC) 12 and a second circuit, such as a first-in first-out FIFO 14. A clock signal CLK is presented to an input 16 of the ASIC 12 and to an input 18 of the FIFO 14. The ASIC 12 presents a data signal DATA to the FIFO 14 in response to the system clock CLK. The FIFO 14 requires an aggressive setup time since both the ASIC 12 and the FIFO 14 are driven by the system clock CLK.
Referring to FIG. 2, a conventional circuit 20 requiring an aggressive data hold time is shown. The circuit 20 comprises a logic block 22 and a FIFO 24. The logic block 22 receives a data signal DATA. Additionally, the logic block 22 presents the data signal DATA and a clock CLK to the FIFO 24. The FIFO 24 requires an aggressive hold time, because the clock CLK and the data presented to the FIFO 24 are serially connected between the logic block 22 and the FIFO 24.
The conventional FIFOs 14 and 24 have non-optimal data setup/hold timing. The conventional FIFOs 14 and 24 are limited, since they introduce performance degradation.